1. Field of the Invention
The present invention relates to a method for forming ultra large scale integration circuits (ULSI), and, more particularly, to a method for a copper-palladium alloy damascene technology applied to the ULSI circuit fabrication.
2. Description of the Prior Art
Copper has become a promising material to replace aluminum for Ultra Large Scale Integration Circuits (ULSI) interconnection due to its better conductivity and reliability. However, several difficulties are encountered owing to the current process flow of dual damascene and inherent physical properties of copper, as illustrated in FIG. 1A to FIG. 1E. First, after the copper gap-fill electroplating, the high temperature furnace annealing suffers low throughput and potential oxidation hazard since copper is easily and quickly oxidized at low temperature, and, unlike aluminum, forms no self-protective oxide layer to prevent further oxidation. Formation of oxide compounds degrades the electrical and mechanical properties of copper. Second, peeling issues between capped Si.sub.3 N.sub.4 barrier and copper/dielectrics may occur because of bad adhesion. Third, for the present etching process to be used, copper will be exposed during the via etching step in opening low conductivity Si.sub.3 N.sub.4 barrier and potentially cause the device degradation.
An example of a typical copper damascene technology for ULSI circuits fabrication process steps is shown in FIG. 1A to FIG. 1E.
Referring to FIG. 1A and FIG 1B, a copper seed 12 is deposited over an oxide layer 10 by means of a barrier TaN 11, and then a copper gap-fill electroplating layer 13 is electroplated over the oxide layer 10, which is used as an inter metal dielectric (IMD) layer 10.
Next, a copper 13 annealing process is carried out in the ambient N.sub.2. So far as is known, copper 13 is an easily oxidation material so the annealing process must proceed in the ambient N.sub.2 to prevent the oxidation reaction, and then unload the device at the low temperature. The temperature reducing period is in terms of oxidation throughput. The higher oxidation throughput means for the higher taking out temperature. By the way, benefits include reducing the annealing time and cost.
Referring to FIG. 1C, a chemical mechanical polishing (CMP) process is carried out by planarizing the copper plating surface 13.
Referring to FIG. 1D, the Si.sub.3 N.sub.4 cap 14 is deposited over the planarized Cu surface 12 to protect it. However, it will face the peeling issues between capped Si.sub.3 N.sub.4 barrier 14 and copper 13/dielectrics 10 which may occur because of bad adhesion.
Referring to FIG. 1E, another inter metal dielectric (IMD) layer 15 is formed over the Si.sub.3 N.sub.4 cap layer 14 of the first IMD layer, and then proceeding the via etching step over the Si.sub.3 N.sub.4 cap layer 14 to connect the first IMD layer 10 and the second IMD layer 15. For the present etching process to be used, copper will be exposed to the IMD layer 15 during the via etching step in opening the low conductivity Si.sub.3 N.sub.4 barrier 14 and potentially cause the device short or degradation owing to the high diffusivity of copper 13.
The above problems are hindrances of copper damascene technology for VLSI circuits progress. Now a copper-palladium method is presented to solve those issues as follows.